UVM RAL Model types, enums and utility classes

This section describes UVM RAL model types, enums and utility classes.

UVM RAL types

uvm_reg_data_t

2-state data value with `UVM_REG_DATA_WIDTH bits

uvm_reg_data_logic_t

4-state data value with `UVM_REG_DATA_WIDTH bits

uvm_reg_addr_t

2-state address value with `UVM_REG_ADDR_WIDTH bits

uvm_reg_addr_logic_t

4-state address value with `UVM_REG_ADDR_WIDTH bits

uvm_reg_byte_en_t

2-state byte_enable value with `UVM_REG_BYTENABLE_WIDTH bits

uvm_reg_cvr_t

Coverage model value set with `UVM_REG_CVR_WIDTH bits

uvm_hdl_path_slice

Slice of an HDL path

UVM RAL Enums

uvm_status_e

Return status for register operations

• UVM_IS_OK
  • Operation completed successfully
• UVM_NOT_OK
  • Operation completed with error
• UVM_HAS_X
  • Operation completed successfully bit had unknown bits.

uvm_path_e

Path used for register operation

• UVM_FRONTDOOR
  • Use the front door
• UVM_BACKDOOR
  • Use the back door
• UVM_PREDICT
  • Operation derived from observations by a bus monitor via the uvm_reg_predictor class
• UVM_DEFAULT_PATH
  • Operation specified by the context

uvm_check_e

Read-only or read-and-check

• UVM_NO_CHECK
  • Read only
• UVM_CHECK
  • Read and check

uvm_endianness_e

Specifies byte ordering

• UVM_NO_ENDIAN
  • Byte ordering not applicable
• UVM_LITTLE_ENDIAN
  • Least-significant bytes first in consecutive addresses
• UVM_BIG_ENDIAN
  • Most-significant bytes first in consecutive addresses
• UVM_LITTLE_FIFO
  • Least-significant bytes first at the same address
• UVM_BIG_FIFO
  • Most-significant bytes first at the same address

uvm_elem_kind_e

Type of element being read or written

• UVM_REG
  • Register
• UVM_FIELD
  • Field
• UVM_MEM
  • Memory location

uvm_access_e

Type of operation begin performed

• UVM_READ
  • Read operation
• UVM_WRITE
  • Write operation

uvm_hier_e

Whether to provide the requested information from a hierarchical context.

• UVM_NO_HIER
  • Provide info from the local context
• UVM_HIER
  • Provide info based on the hierarchical context

uvm_predict_e

How the mirror is to be updated

• UVM_PREDICT_DIRECT
  • Predicted value is as-is
• UVM_PREDICT_READ
  • Predict based on the specified value having been read
• UVM_PREDICT_WRITE
  • Predict based on the specified value having been written

uvm_coverage_model_e

Coverage models available or desired.  Multiple models may be specified by bitwise
OR’ing individual model identifiers.

• UVM_NO_COVERAGE
  • None
• UVM_CVR_REG_BITS
  • Individual register bits
• UVM_CVR_ADDR_MAP
  • Individual register and memory addresses
• UVM_CVR_FIELD_VALS
  • Field values
• UVM_CVR_ALL
  • All coverage models

uvm_reg_mem_tests_e

Select which pre-defined test sequence to execute. Multiple test sequences may be selected by bit-wise OR’ing their respective symbolic values.

• UVM_DO_REG_HW_RESET
  • Run uvm_reg_hw_reset_seq
• UVM_DO_REG_BIT_BASH
  • Run uvm_reg_bit_bash_seq
• UVM_DO_REG_ACCESS
  • Run uvm_reg_access_seq
• UVM_DO_MEM_ACCESS
  • Run uvm_mem_access_seq
• UVM_DO_SHARED_ACCESS
  • Run uvm_reg_mem_shared_access_seq
• UVM_DO_MEM_WALK
  • Run uvm_mem_walk_seq
• UVM_DO_ALL_REG_MEM_TESTS
  • Run all of the above

Test sequences, when selected, are executed in the order in which they are specified
above.
❮ Previous Next ❯