UVM Phases

 UVM Phases 

UVM Phases are a synchronizing mechanism for the environment.

Phases are represented by callback methods, A set of predefined phases and corresponding callbacks are provided in uvm_component. The Method can be either function or task.

Any class deriving from uvm_component may implement any or all of these callbacks, which are executed in a particular order. 

The UVM Phases are,
  • build 
  • connect 
  • end of elaboration
  • start of simulation
  • run
  • extract
  • check 
  • report

run phase is implemented as task and remaining all are function.

Phases can be grouped into 3 categories,

1. Build Phases
build phase, connect phase and end_of_elobaration phase's belong to this category.
Phases in this categorize are executed at the start of the UVM testbench simulation, where the testbench components are constructed, configured and testbench components are connected.

All the build phase methods are functions and therefore execute in zero simulation time.

*click on image for better view
2. Run-time Phases
start of simulation and run phase belongs to run-time phases, run phase will get executed from start of simulation to till the end of simulation.
run phase is time consuming, where the testcase is running.

3. Clean up Phases
extract, check, report and final belong to this category.
where the results of the testcase are collected and reported. example: number of error's during the simulation are reported.

 Phases Description: 

Execution Order
Used to construct the testbench components.
Used to connect TLM ports of components.
Used to make any final adjustments to the structure, configuration or connectivity of the testbench before simulation starts.
used for printing testbench topology or configuration information.
Used for stimulus generation, driving, monitoring and checking.
Used to retrieve and process information from scoreboards and functional coverage monitors.

Used to check that the DUT behaved correctly and to identify any errors that may have occurred during the execution of the test bench.

Used to display the results of the simulation or to write the results to file.

Used to complete any other outstanding actions that the test bench has not already completed.

run phase has different phases, these are,

pre_reset phase starts at the same time as the run phase. Its purpose is to take care of any activity that should occur before reset, such as waiting for a power-good signal to go active.
The reset phase is reserved for DUT or interface specific reset behavior. For example, this phase would be used to generate a reset and to put an interface into its default state.
Intended for any activity required immediately following reset.
pre_configure phase is intended for anything that is required to prepare for the DUT's configuration process after reset is completed
configure phase is used to program the DUT and any memories in the testbench so that it is ready for the start of the test case.
post_configure phase is used to wait for the effects of configuration to propagate through the DUT, or for it to reach a state where it is ready to start the main test stimulus.
pre_main phase is used to ensure that all required components are ready to start generating stimulus.
This is where the stimulus specified by the test case is generated and applied to the DUT. It completes when either all stimulus is exhausted or a timeout occurs.
This phase is used to take care of any finalization of the main phase.
This phase is a buffer for any DUT stimulus that needs to take place before the shutdown phase.
The shutdown phase is used to ensure that the effects of the stimulus generated during the main phase have propagated through the DUT and that any resultant data has drained away.
Perform any final activities before exiting the active simulation phases. At the end of the post_shutdown phase, the UVM testbench execution process starts the clean up phases.