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uvm_event wait trigger data

uvm_event with parameter data type


The uvm_event defined with the optional parameter T allows the user to define a data type that can be passed during an event trigger.

This is one of the key benefits of uvm_event. Along with the event triggering, data can be passed, this data can be retrieved at wait for the event trigger.

Syntax to declare


uvm_event#(T)
// T - user defined data type

uvm_event class declaration in uvm library,
class uvm_event#(
type T = uvm_object
) extends uvm_event_base

Note:
T is of  uvm_object type, passing the type other than uvm_object leads to a compilation error.

Methods


  • new 
    • Creates a new event object
  • trigger 
    • Triggers the event, resuming all waiting processes.
  • get_trigger_data
    • Gets the data, if any, provided by the last call to trigger
  • wait_trigger_data
    • This method calls uvm_event_base::wait_trigger followed by get_trigger_data
  • wait_ptrigger_data
    • This method calls uvm_event_base::wait_ptrigger followed by get_trigger_data

uvm_event with parameter example


The below example consists of two components comp_a and comp_b. comp_a will trigger an event and comp_b wait for the event trigger. Along with the event trigger, comp_a will randomize the transaction object trans and send it to the comp_b via event trigger.

Below are the methods used in this example,

  • ev.trigger(trans) - triggers an event and send the trans.
  • ev.wait_trigger   - wait for an event trigger.
  • ev.get_trigger_data() - retrive the data from event trigger.
  • $cast(trans,ev.get_trigger_data()) - return type of get_trigger_data is object, $cast is used for assignment.




comp_a code  


  //---------------------------------------
  // run_phase 
  //---------------------------------------
  virtual task run_phase(uvm_phase phase);
    phase.raise_objection(this);
    
    #10;
    trans = transaction::type_id::create("trans", this);
    
    trans.randomize();
    `uvm_info(get_type_name(),$sformatf(" randomized trans, \n %s",
                                          trans.sprint()),UVM_LOW)
    
    ev = uvm_event_pool::get_global("ev_ab"); //Step-1. get event from global pool
    
    `uvm_info(get_type_name(),$sformatf(" Before triggering the event"),UVM_LOW)
    
    ev.trigger(trans); //Step-2. trigger an event and send trans
    
    `uvm_info(get_type_name(),$sformatf(" After triggering the event"),UVM_LOW)

    phase.drop_objection(this);
  endtask : run_phase

comp_b code


  //---------------------------------------
  // run_phase 
  //---------------------------------------
  virtual task run_phase(uvm_phase phase);
    phase.raise_objection(this); 
    
    ev = uvm_event_pool::get_global("ev_ab"); //Step-1. get event from global pool
    
    `uvm_info(get_type_name(),$sformatf(" waiting for the event trigger"),UVM_LOW)
    
    ev.wait_trigger; //Step-2. wait for an event trigger
    
    `uvm_info(get_type_name(),$sformatf(" event got triggerd"),UVM_LOW)
    
    $cast(trans,ev.get_trigger_data()); //Step-3. retrive the data from event trigger
    `uvm_info(get_type_name(),$sformatf(" trans received, \n %s",trans.sprint()),UVM_LOW)

    phase.drop_objection(this);
  endtask : run_phase

 Simulator Output 

UVM_INFO @ 0: reporter [RNTST] Running test basic_test...
--------------------------------------
Name Type Size Value
--------------------------------------
uvm_test_top basic_test - @335
comp_a component_a - @348
comp_b component_b - @357
--------------------------------------
UVM_INFO component_b.sv(27) @ 0: uvm_test_top.comp_b [component_b] waiting for the event trigger
UVM_INFO component_a.sv(29) @ 10: uvm_test_top.comp_a [component_a] randomized trans,
---------------------------------
Name Type Size Value
---------------------------------
trans transaction - @392
addr integral 4 'hb
wr_rd integral 1 'h1
wdata integral 8 'h54
---------------------------------

UVM_INFO component_a.sv(33) @ 10: uvm_test_top.comp_a [component_a] Before triggering the event
UVM_INFO component_a.sv(37) @ 10: uvm_test_top.comp_a [component_a] After triggering the event
UVM_INFO component_b.sv(31) @ 10: uvm_test_top.comp_b [component_b] event got triggerd
UVM_INFO component_b.sv(34) @ 10: uvm_test_top.comp_b [component_b] trans received,
---------------------------------
Name Type Size Value
---------------------------------
trans transaction - @392
addr integral 4 'hb
wr_rd integral 1 'h1
wdata integral 8 'h54
---------------------------------

UVM_INFO /apps/vcsmx/etc/uvm-1.2/src/base/uvm_objection.svh(1270) @ 10: reporter [TEST_DONE]
UVM_INFO /apps/vcsmx/etc/uvm-1.2/src/base/uvm_report_server.svh(847) @ 10: reporter [UVM/REPORT/SERVER]

Execute the above code on 

uvm_event with parameter type int


In the below example, the int type is passed along with the event trigger. As seen above passing a data type other than uvm_object leads to a compilation error.

  //---------------------------------------
  // run_phase 
  //---------------------------------------
  virtual task run_phase(uvm_phase phase);
    phase.raise_objection(this);
    
    ev  = uvm_event_pool::get_global("ev_ab");
    
    `uvm_info(get_type_name(),$sformatf(" Before triggering the event"),UVM_LOW)
    
    ev.trigger(30);
    
    `uvm_info(get_type_name(),$sformatf(" After triggering the event"),UVM_LOW)

    phase.drop_objection(this);
  endtask : run_phase

 Simulator Output 

ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog
simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
ev.trigger(30);
|
ncelab: *E,TYCMPAT (./component_a.sv,28|16): formal and actual do not have assignment compatible
data types (expecting datatype compatible with 'class uvm_pkg::uvm_object' but found 'integer' instead).
irun: *E,ELBERR: Error during elaboration (status 1), exiting.
Exit code expected: 0, received: 1

Execute the above code on