Connecting TLM Port Port Imp port

Port Port Imp_port

This example shows connecting TLM Port -> Port -> Imp_port.

TLM TesetBench Components are,

---------------------------------------------------------------
Name Type
---------------------------------------------------------------
uvm_test_top basic_test
    env environment
    comp_a component_a
sub_comp_a_a sub_component_a_a
trans_out uvm_blocking_put_port
    trans_out uvm_blocking_put_port
    comp_b component_b
    trans_in uvm_blocking_put_imp
---------------------------------------------------------------

Implement TLM port in sub_comp_a_a

Implementing TLM port in sub_comp_a_a involves below steps,

Declare the uvm_blocking_put_port
Create the port
Randomize the transaction class
Send the transaction to the comp_b through put() method

class sub_component_a_a extends uvm_component;

  //Step-1. Declaring blocking port
  uvm_blocking_put_port #(transaction) trans_out;
  
  `uvm_component_utils(sub_component_a_a)
  
  //--------------------------------------- 
  // Constructor
  //---------------------------------------
  function new(string name, uvm_component parent);
    super.new(name, parent);
    trans_out = new("trans_out", this);  //Step-2. Creating the port
  endfunction : new

  //---------------------------------------
  // run_phase 
  //---------------------------------------
  virtual task run_phase(uvm_phase phase);
    phase.raise_objection(this);
    
    trans = transaction::type_id::create("trans", this);

    void'(trans.randomize());  //Step-3. randomizing the transction

    `uvm_info(get_type_name(),$sformatf(" tranaction randomized"),UVM_LOW)
    `uvm_info(get_type_name(),$sformatf(" Printing trans, 
                                          \n %s",trans.sprint()),UVM_LOW)
    
    `uvm_info(get_type_name(),$sformatf(" Before calling port put method"),UVM_LOW)

    trans_out.put(trans);  //Step-4. Sending trans through port put method

    `uvm_info(get_type_name(),$sformatf(" After  calling port put method"),UVM_LOW)
    
    phase.drop_objection(this);
  endtask : run_phase

endclass : sub_component_a_a

Implement TLM port in comp_a

Implementing TLM port in comp_a involves below steps,

Declare the uvm_blocking_put_port
Create the port
Connect port with sub_comp_a_a port

class component_a extends uvm_component;
  
  sub_component_a_a sub_comp_a_a;

  //Step-1. Declaring blocking port 
  uvm_blocking_put_port#(transaction) trans_out;  

  `uvm_component_utils(component_a)
  
  //--------------------------------------- 
  // Constructor
  //---------------------------------------
  function new(string name, uvm_component parent);
    super.new(name, parent);
    trans_out = new("trans_out", this);  //Step-2. Creating the port 
  endfunction : new
  
  //---------------------------------------
  // build_phase - Create the components
  //---------------------------------------
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);

    sub_comp_a_a = sub_component_a_a::type_id::create("sub_comp_a_a", this);
  endfunction : build_phase
  
  //---------------------------------------
  // Connect_phase 
  //---------------------------------------
  function void connect_phase(uvm_phase phase);
    sub_comp_a_a.trans_out.connect(trans_out);  //Step-3. Connecting port with sub_comp_a_a port 
  endfunction : connect_phase
endclass : component_a

Implement TLM Imp port in comp_b

Implementing TLM Imp port in comp_b involves below steps,

Declare the uvm_blocking_put_imp
Create the imp port
Implement the put() method to receive the transaction

class comp_b extends uvm_component;
  
  transaction trans;

  //Step-1. Declaring blocking imp port  
  uvm_blocking_put_imp#(transaction,comp_b) trans_in;  

  `uvm_component_utils(compo_b)
  
  //--------------------------------------- 
  // Constructor
  //---------------------------------------
  function new(string name, uvm_component parent);
    super.new(name, parent);
    trans_in = new("trans_in", this);  //Step-2. Creating imp port
  endfunction : new
  
  //---------------------------------------
  // Imp port put method
  //---------------------------------------
  //Step-3. Implementing imp port
  virtual task put(transaction trans);
    `uvm_info(get_type_name(),$sformatf(" Recived trans On IMP Port"),UVM_LOW)
    `uvm_info(get_type_name(),$sformatf(" Printing trans, 
                                          \n %s",trans.sprint()),UVM_LOW)
  endtask 

endclass : comp_b

Environment code

In the environment file comp_a port is connected with the comp_b export.

  function void connect_phase(uvm_phase phase);
    comp_a.trans_out.connect(comp_b.trans_in);  //Connecting port with export 
  endfunction : connect_phase

Simulator Output

UVM_INFO @ 0: reporter [RNTST] Running test basic_test...
------------------------------------------------------
Name Type Size Value
------------------------------------------------------
uvm_test_top basic_test - @1842
env environment - @1911
comp_a component_a - @1943
sub_comp_a_a sub_component_a_a - @2041
trans_out uvm_blocking_put_port - @2113
trans_out uvm_blocking_put_port - @1978
comp_b component_b - @2011
trans_in uvm_blocking_put_imp - @2046
------------------------------------------------------
UVM_INFO sub_component_a_a.sv(29) @ 0: uvm_test_top.env.comp_a.sub_comp_a_a [sub_component_a_a] tranaction randomized
UVM_INFO sub_component_a_a.sv(30) @ 0: uvm_test_top.env.comp_a.sub_comp_a_a [sub_component_a_a] Printing trans,
---------------------------------
Name Type Size Value
---------------------------------
trans transaction - @2151
addr integral 4 'h2
wr_rd integral 1 'h1
wdata integral 8 'h9d
---------------------------------

UVM_INFO sub_component_a_a.sv(32) @ 0: uvm_test_top.env.comp_a.sub_comp_a_a [sub_component_a_a] Before calling port put method
UVM_INFO component_b.sv(24) @ 0: uvm_test_top.env.comp_b [component_b] Recived trans On IMP Port
UVM_INFO component_b.sv(25) @ 0: uvm_test_top.env.comp_b [component_b] Printing trans,
---------------------------------
Name Type Size Value
---------------------------------
trans transaction - @2151
addr integral 4 'h2
wr_rd integral 1 'h1
wdata integral 8 'h9d
---------------------------------

UVM_INFO sub_component_a_a.sv(34) @ 0: uvm_test_top.env.comp_a.sub_comp_a_a [sub_component_a_a] After calling port put method
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_objection.svh(1271) @ 0: reporter [TEST_DONE]
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_report_server.svh(847) @ 0: reporter [UVM/REPORT/SERVER]

Execute the above code on

Contact / Report an issue

TLM Port Port Imp Port Connection