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TLM Get port imp port

Connecting TLM Get port imp port


UVM TLM Get Port Get Imp port
TLM Get Port Get Imp port
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This example shows connection TLM get port and get imp port.

In the components with TLM put ports,
  • The producer component initiates the transaction and sends it to consumer component
  • The producer component will be implemented with TLM put port and Consumer component with TLM imp_port
  • put method has to be implemented in the consumer

Whereas in with TLM get ports,
  • The consumer component will request for the transaction
  • The consumer component will be implemented with TLM get port and Producer with TLM imp_port
  • get method has to be implemented in the producer

Below are the steps to implement a TLM get port between comp_a and comp_b.
  1. Declare and Create TLM Get Port in comp_b
  2. Declare and Create TLM Imp Port in comp_a
  3. Connect TLM Port and Imp Port in env
  4. Call interface method in comp_b to get the transaction
  5. Implement an interface method in comp_a to randomize and send the transaction 

TLM Get port TesetBench Components are,


---------------------------------------------------------------
Name                Type                 
---------------------------------------------------------------
uvm_test_top              basic_test           
    env                          environment         
      comp_a                 component_a         
          trans_out           uvm_blocking_get_imp
      comp_b                 component_b         
          trans_in             uvm_blocking_get_port
---------------------------------------------------------------

Implementing TLM get port in comp_b (Consumer)


class component_b extends uvm_component;
  
  transaction trans;

  //Step-1. Declaring TLM Get port
  uvm_blocking_get_port#(transaction) trans_in;  

  `uvm_component_utils(component_b)
  
  //--------------------------------------- 
  // Constructor
  //---------------------------------------
  function new(string name, uvm_component parent);
    super.new(name, parent);
    trans_in = new("trans_in", this); //Step-2. Creating port
  endfunction : new 
  
  //---------------------------------------
  // run_phase 
  //---------------------------------------
  virtual task run_phase(uvm_phase phase);
    phase.raise_objection(this);

    `uvm_info(get_type_name(),$sformatf(" Requesting transaction."),UVM_LOW)
    
    `uvm_info(get_type_name(),$sformatf(" Before calling port get method"),UVM_LOW)

    //Step-3. Calling TLM get mehtod to recieve transaction from comp_a
    trans_in.get(trans);   

    `uvm_info(get_type_name(),$sformatf(" After  calling port get method"),UVM_LOW)
    trans.print();
    
    phase.drop_objection(this);
  endtask : run_phase
  
endclass : component_b

Implementing TLM get imp port in comp_a (Producer)


class component_a extends uvm_component;

  //Step-1. Declaring TLM Get Imp_port  
  uvm_blocking_get_imp#(transaction,component_a) trans_out; 
  
  `uvm_component_utils(component_a)
  
  //--------------------------------------- 
  // Constructor
  //---------------------------------------
  function new(string name, uvm_component parent);
    super.new(name, parent);
    trans_out = new("trans_out", this);  //Step-2. Creating port
  endfunction : new

  //---------------------------------------
  // Imp port put method
  //---------------------------------------

  //Step-3. Get Method, randomize and send the trans to comp_b
  virtual task get(output transaction trans);
    
    `uvm_info(get_type_name(),$sformatf(" Recived transaction imp port
                                          get request"),UVM_LOW)
    trans = transaction::type_id::create("trans", this);
    
    void'(trans.randomize());
    `uvm_info(get_type_name(),$sformatf(" tranaction randomized"),UVM_LOW)
    `uvm_info(get_type_name(),$sformatf(" Printing trans, \n %s",
                                          trans.sprint()),UVM_LOW)

    `uvm_info(get_type_name(),$sformatf(" Sendting trans packet"),UVM_LOW)
  endtask   
endclass : component_a




Connecting get port with get imp port in env


  function void connect_phase(uvm_phase phase);
    comp_b.trans_in.connect(comp_a.trans_out); //Connecting port with imp_port
  endfunction : connect_phase

 Simulator Output 

UVM_INFO @ 0: reporter [RNTST] Running test basic_test...
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
uvm_test_top basic_test - @1839
env environment - @1908
comp_a component_a - @1940
trans_out uvm_blocking_get_imp - @1975
comp_b component_b - @2008
trans_in uvm_blocking_get_port - @2043
---------------------------------------------------
UVM_INFO component_b.sv(26) @ 0: uvm_test_top.env.comp_b [component_b] Requesting transaction.
UVM_INFO component_b.sv(28) @ 0: uvm_test_top.env.comp_b [component_b] Before calling port get method
UVM_INFO component_a.sv(24) @ 0: uvm_test_top.env.comp_a [component_a] Recived transaction imp port get request
UVM_INFO component_a.sv(28) @ 0: uvm_test_top.env.comp_a [component_a] tranaction randomized
UVM_INFO component_a.sv(29) @ 0: uvm_test_top.env.comp_a [component_a] Printing trans,
---------------------------------
Name Type Size Value
---------------------------------
trans transaction - @1135
addr integral 4 'ha
wr_rd integral 1 'h0
wdata integral 8 'h57
---------------------------------

UVM_INFO component_a.sv(31) @ 0: uvm_test_top.env.comp_a [component_a] Sendting trans packet
UVM_INFO component_b.sv(30) @ 0: uvm_test_top.env.comp_b [component_b] After calling port get method
---------------------------------
Name Type Size Value
---------------------------------
trans transaction - @1135
addr integral 4 'ha
wr_rd integral 1 'h0
wdata integral 8 'h57
---------------------------------
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_objection.svh(1271) @ 0: reporter [TEST_DONE]
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_report_server.svh(847) @ 0: reporter [UVM/REPORT/SERVER]

Execute the above code on