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TLM Analysis FIFO example

TLM Analysis FIFO


 UVM TLM Analysis FIFO
UVM TLM Analysis FIFO

TLM Analysis FIFO enables the implementing of FIFO in consumers and connects it directly to the analysis port. This example shows a connecting analysis port to an analysis FIFO.

TLM Analysis FIFO TesetBench Components are,


----------------------------------------------------------------
Name                     Type                     
----------------------------------------------------------------
uvm_test_top                    basic_test               
  env                                  environment               
    comp_a                         component_a               
         analysis_port           uvm_analysis_port         
    comp_b                         component_b               
         analy_fifo                uvm_tlm_analysis_fifo #(T)
           analysis_export     uvm_analysis_imp         
           get_ap                    uvm_analysis_port       
           get_peek_export    uvm_get_peek_imp         
           put_ap                    uvm_analysis_port         
           put_export             uvm_put_imp             
----------------------------------------------------------------

Implementing analysis port in comp_a


class component_a extends uvm_component;
  
  transaction trans;

  //Step-1. Declaring analysis port
  uvm_analysis_port#(transaction) analysis_port; 
  
  `uvm_component_utils(component_a)
  
  //--------------------------------------- 
  // Constructor
  //---------------------------------------
  function new(string name, uvm_component parent);
    super.new(name, parent);
    
    //Step-2. Creating analysis port
    analysis_port = new("analysis_port", this); 
  endfunction : new

  //---------------------------------------
  // run_phase 
  //---------------------------------------
  virtual task run_phase(uvm_phase phase);
    phase.raise_objection(this);
    
    trans = transaction::type_id::create("trans", this);

    void'(trans.randomize());
    `uvm_info(get_type_name(),$sformatf(" tranaction randomized"),UVM_LOW)
    `uvm_info(get_type_name(),$sformatf(" Printing trans, \n %s",
                                          trans.sprint()),UVM_LOW)
    
    `uvm_info(get_type_name(),$sformatf(" Before calling port write method"),UVM_LOW)

    //Ste-3. Calling write method
    analysis_port.write(trans);
    `uvm_info(get_type_name(),$sformatf(" After  calling port write method"),UVM_LOW)
    
    phase.drop_objection(this);
  endtask : run_phase
endclass : component_a




Implementing analysis FIFO in comp_b


class component_b extends uvm_component;
  
  transaction trans;

  //Step-1. Declaring analysis FIFO
  uvm_tlm_analysis_fifo #(transaction) analy_fifo;   

  `uvm_component_utils(component_b)
  
  //--------------------------------------- 
  // Constructor
  //---------------------------------------
  function new(string name, uvm_component parent);
    super.new(name, parent);

    //Step-2. Creating analysis FIFO
    analy_fifo = new("analy_fifo", this);
  endfunction : new
  
  //---------------------------------------
  // run_phase 
  //---------------------------------------
  virtual task run_phase(uvm_phase phase);
    phase.raise_objection(this);
    
    #100;
    `uvm_info(get_type_name(),$sformatf(" Before calling analysis fifo get method"),UVM_LOW)

    //Step.3 - Getting trans from FIFO
    analy_fifo.get(trans);

    `uvm_info(get_type_name(),$sformatf(" After  calling analysis fifo get method"),UVM_LOW)
    `uvm_info(get_type_name(),$sformatf(" Printing trans, \n %s",trans.sprint()),UVM_LOW)
    
    phase.drop_objection(this);
  endtask : run_phase

endclass : component_b




Connecting analysis port and analysis FIFO in env


  function void connect_phase(uvm_phase phase);

    //Connecting analysis port to analysis FIFO
    comp_a.analysis_port.connect(comp_b.analy_fifo.analysis_export);
  endfunction : connect_phase

 Simulator Output 

UVM_INFO @ 0: reporter [RNTST] Running test basic_test...
----------------------------------------------------------------
Name Type Size Value
----------------------------------------------------------------
uvm_test_top basic_test - @1841
env environment - @1910
comp_a component_a - @1942
analysis_port uvm_analysis_port - @1977
comp_b component_b - @2010
analy_fifo uvm_tlm_analysis_fifo #(T) - @2008
analysis_export uvm_analysis_imp - @2217
get_ap uvm_analysis_port - @2181
get_peek_export uvm_get_peek_imp - @2111
put_ap uvm_analysis_port - @2146
put_export uvm_put_imp - @2076
----------------------------------------------------------------
UVM_INFO component_a.sv(29) @ 0: uvm_test_top.env.comp_a [component_a] tranaction randomized
UVM_INFO component_a.sv(30) @ 0: uvm_test_top.env.comp_a [component_a] Printing trans,
---------------------------------
Name Type Size Value
---------------------------------
trans transaction - @2273
addr integral 4 'he
wr_rd integral 1 'h0
wdata integral 8 'h4
---------------------------------

UVM_INFO component_a.sv(32) @ 0: uvm_test_top.env.comp_a [component_a] Before calling port write method
UVM_INFO component_a.sv(34) @ 0: uvm_test_top.env.comp_a [component_a] After calling port write method
UVM_INFO component_b.sv(27) @ 100: uvm_test_top.env.comp_b [component_b] Before calling analysis fifo get method
UVM_INFO component_b.sv(29) @ 100: uvm_test_top.env.comp_b [component_b] After calling analysis fifo get method
UVM_INFO component_b.sv(30) @ 100: uvm_test_top.env.comp_b [component_b] Printing trans,
---------------------------------
Name Type Size Value
---------------------------------
trans transaction - @2273
addr integral 4 'he
wr_rd integral 1 'h0
wdata integral 8 'h4
---------------------------------

UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_objection.svh(1271) @ 100: reporter [TEST_DONE]
UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_report_server.svh(847) @ 100: reporter [UVM/REPORT/SERVER]

Execute the above code on