SystemVerilog typedef classes

 typedef classes 


In some cases class variable needs to be declared before the class declaration.in this type of situation typedef is used to provide a forward declaration of the class.

 Example-1: 

In the Example Below,
There are two classes c1 and c2, class c1 need handle of class c2 and class c1 need handle of class2. this problem is resolved using typedef.

delete/Comment the typedef class c2; line and check, you will get compilation error saying c2 is undeclared.

typedef class c2;
//class-1
class c1;
  c2 c;    //using class c2 handle before declaring it.
endclass

//class-2
class c2;
  c1 c;
endclass
 
module typedef_class;
  initial begin
    c1 class1;
    c2 class2;
  end
endmodule

Execute the above code on