SystemVerilog typedef class

typedef class


A typedef is used to provide a forward declaration of the class.

In some cases, the class needs to be instantiated before the class declaration. In these kinds of situations, the typedef is used to provide a forward declaration of the class.

typedef syntax


typedef class class_name;

typedef examples 


Without typedef


In the below example,
There are two classes c1 and c2.
c2 is instantiated inside c1 and c1 inside c2. Both classes need the handle of each other. As execution will happen in sequential order.

Dependency between both the classes leads to a compilation error.

//class-1
class c1;
  c2 c;    //using class c2 handle before declaring it.
endclass

//class-2
class c2;
  c1 c;
endclass
 
module typedef_class;
  initial begin
    c1 class1;
    c2 class2;
    $display("Inside typedef_class");
  end
endmodule

 Simulator Output 

Error-[SE] Syntax error
  Following verilog source has syntax error :
  token 'c2' should be a valid type. Please declare it virtual if it
  is an Interface.
  "testbench.sv", 6: token is ';'
    c2 c;

Execute the above code on 



With typedef


The compilation error of the above example can be avoided by using a typedef.

typedef class c2;
//class-1
class c1;
  c2 c;    //using class c2 handle before declaring it.
endclass

//class-2
class c2;
  c1 c;
endclass
 
module typedef_class;
  initial begin
    c1 class1;
    c2 class2;
    $display("Inside typedef_class");
  end
endmodule

 Simulator Output 

Inside typedef_class
Execute the above code on