SystemVerilog TestBench Example -- Adder

Lets Write the SystemVerilog TestBench for the simple design "ADDER".

Before writing the SystemVerilog TestBench, will look into the design specification.

Below is the block diagram of ADDER.

"Adder" Design block diagram
Adder is,
  • fed with the inputs clock, reset, a, b and valid.
  • has output is c.

Valid signal indicates the valid value on the a and b, On valid signal adder will add the a and b, drives the result in next clock on c.

Adder add/Sum the 4bit values 'a' and 'b', and drives the result on c in the next clock.

waveform diagram:

"Adder" Waveform 
waveform snapshot from: EPWave - EDAPlayground

For the simplicity and easy of understanding, lets write the two TestBecnh's,