SystemVerilog Tasks

tasks


Tasks and Functions provide a means of splitting code into small parts.

A Task can contain a declaration of parameters, input arguments, output arguments, in-out arguments, registers, events and zero or more behavioral statements.

SystemVerilog task can be,

  • static
  • automatic

Static tasks


Static tasks share the same storage space for all task calls.

Automatic tasks


Automatic tasks allocate unique, stacked storage for each task call.

SystemVerilog allows,
  • to declare automatic variable in static task and static variable in automatic task
  • more capabilities for declaring task ports
  • multiple statements within task without requiring a begin...end or fork...join block
  • returning from task before reaching the end of task
  • passing values by reference, value, names and position
  • default argument values
  • default direction of argument is input if no direction has been specified
  • default arguments type is logic if no type has been specified

task examples

task arguments in parentheses


module sv_task;
  int x;

  //task to add two integer numbers.
  task sum(input int a,b,output int c);
    c = a+b;   
  endtask

  initial begin
    sum(10,5,x);
    $display("\tValue of x = %0d",x);
  end
endmodule


 Simulator output: 
       Value of x=15
Execute the above code on 




task arguments in declarations and mentioning directions


module sv_task;
  int x;

  //task to add two integer numbers.
  task sum;
    input int a,b;
    output int c;
    c = a+b;   
  endtask

  initial begin
    sum(10,5,x);
    $display("\tValue of x = %0d",x);
  end
endmodule


 Simulator output: 
       Value of x = 15
Execute the above code on