SystemVerilog Tasks

 tasks 


Tasks and Functions provide a means of splitting code into small parts.
A Task can contain a declaration of parameters, input arguments, output arguments, in-out arguments, registers, events and zero or more behavioral statements.

SystemVerilog task can be static or automatic.Static tasks share the same storage space for all task calls.Automatic tasks allocate unique, stacked storage for each task call.

SystemVerilog allows,
1.to declare automatic variable in static task and static variable in automatic task
 2.more capabilities for declaring task ports
3.multiple statements within task without requiring a begin...end or fork...join block
 4.returning from task before reaching the end of task
 5.Passing values by reference, value, names and position
 6.Default argument values
 7.Default direction of argument is input if no direction has been specified.
 8.Default arguments type is logic if no type has been specified.


  Example-1:  

In the below example,
arguments in parentheses.

module sv_task;
  int x;

  //task to add two integer numbers.
  task sum(input int a,b,output int c);
    c = a+b;   
  endtask

  initial begin
    sum(10,5,x);
    $display("\tValue of x = %0d",x);
  end
endmodule


  Simulator output:  
       Value of x=15
Execute the above code on 

  Example-2:  

In below example,
arguments in declarations and directions.

module sv_task;
  int x;

  //task to add two integer numbers.
  task sum;
    input int a,b;
    output int c;
    c = a+b;   
  endtask

  initial begin
    sum(10,5,x);
    $display("\tValue of x = %0d",x);
  end
endmodule


  Simulator output:  
       Value of x = 15
Execute the above code on