SystemVerilog Super keyword

 Super keyword 

The super keyword is used in a derived class to refer to members of the parent class. It is necessary to use super to access members of a parent class when those members are overridden by the derived class.

In child class, method with the same name of parent class will override the method.by using super keyword parent class method can be accessed from child class.

 Example - 1 

parent class method display is overridden in the child class, by calling super.display() from child class display method of parent class can be accessed.

class parent_class;
  bit [31:0] addr;

  function display();
    $display("Addr = %0d",addr);
  endfunction
endclass

class child_class extends parent_class;
  bit [31:0] data;

  function display();
    super.display();
    $display("Data = %0d",data);
  endfunction

endclass

module inheritence;
  initial begin
    child_class c=new();
    c.addr = 10;
    c.data = 20;
    c.display();
  end
endmodule

 Simulator Output  
Addr = 10
Data = 20
Execute the above code on