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SystemVerilog Soft Constraints

Soft Constraints


SystemVerilog constraints declared with the keyword soft is called as soft constraints. any conflict between class constraint and inline constraint leads to a randomization failure, from this it is clear that it is not possible to override the class constraint by inline constraint. Some test scenarios demand to override the constraints, this can be done by writing a soft keyword in class constraint.
A soft constraint is a constraint on a random variable, which allows overriding the constraint.

constraint c_name { soft variable { condition }; }

real-time use of soft constraint


This is one of the situations where soft constraints are useful. Lets Consider, In a verification testbench transaction class constraint is written to generate normal stimulus. For error stimulus generation, error testcase need to have an inline constraint that may conflict with the constraint defined inside the class. In this situation, we have only the option to change the constraint defined inside the transaction class, but changing the constraint in the transaction class will reflect in all other test cases. so this kind of problem can be avoided using soft constraints.

soft constraint examples


Conflict between constraints


In the example below, In the class packet, the addr variable is constrained to greater than 6 and the same addr variable is constrained to less than 6 in the inline constraint. that means expecting the value of addr to be less than and greater than 6, this is not possible and leads to a randomization failure. this problem is resolved in the next example using soft constraint.
class packet;
  rand bit [3:0] addr;
  constraint addr_range { addr > 6; } 
endclass

module soft_constr;
  initial begin
    packet pkt;
    pkt = new();

    repeat(2) begin
      pkt.randomize() with { addr < 6;};
      $display("\taddr = %0d",pkt.addr);
    end
  end
endmodule

 Simulator Output 

Constraints inconsistency failure
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewritethem.
addr = 0

Execute the above code on 



Using soft constraint


In the example below,
a previous example problem is solved using soft constraints,
Constraint declared inside the class will get suppressed by inline constraints.

class packet;
  rand bit [3:0] addr;
  constraint addr_range { soft addr > 6; } 
endclass

module soft_constr;
  initial begin
    packet pkt;
    pkt = new();

    repeat(2) begin
      pkt.randomize() with { addr < 6;};
      $display("\taddr = %0d",pkt.addr);
    end
  end
endmodule

 Simulator Output 

addr = 1
addr = 3

Execute the above code on