SystemVerilog Repetition operators

 Repetition Operators 


property p;
  @(posedge clk) a |-> ##1 b ##1 b ##1 b;
endproperty
a: assert property(p);

The above property checks that, if the signal “a” is high on given posedge of clock, then signal “b” should be high for 3 consecutive clock cycles.

The Consecutive repetition operator is used to specify that a signal or a sequence will match continuously for the number of clocks specified.

Syntax
signal [*n] or sequence [*n]

"n" is the number of  repetitions.

with repetition operator above sequence can be re-written as,

property p;
  @(posedge clk) a |-> ##1 b[*3];
endproperty
a: assert property(p);

Execute the above code on 


 go-to repetition 

The go-to repetition operator is used to specify that a signal will match  the number of times specified not necessarily on continuous clock cycles.

Signal [->n]

property p;
  @(posedge clk) a |-> ##1 b[->3] ##1 c;
endproperty
a: assert property(p);

Execute the above code on 

the above property checks that, if the signal “a” is high on given posedge of clock, then signal “b” should be high for 3 clock cycles followed by “c” should be high after ”b” is high for third time.

 Non-consecutive repetition 

This is very similar to "go to" repetition except that it does not require that the last match on the signal repetition happen in the clock cycle before the end the entire sequence matching.

Signal [=n]

Only expressions are allowed to repeat in "go to" and "nonconsecutive" repetitions. Sequences are not allowed.