SystemVerilog repeat and forever loop

 repeat loop 


repeat will executes the statements with in the loop for loop variable number of times.

  Example-1:  



module repeat_loop;
  int a;
  initial begin
    $display("-----------------------------------------------------------------");

    repeat(4) begin
        $display("\tValue of a=%0d",a);
        a++;
     end
    $display("-----------------------------------------------------------------");
  end   
endmodule


  Simulator output:  
     -----------------------------------------------------------------
          Value of a=0
          Value of a=1
          Value of a=2
          Value of a=3
     -----------------------------------------------------------------
Execute the above code on 


  forever loop 


As the name says forever loop will executes the statements inside the loop forever.

  Example-1:  



module forever_loop;
  int a;
  initial begin
    $display("-----------------------------------------------------------------");
 
    forever begin
      $display("\tValue of a=%0d",a);
      a++;
      #5;
    end
 
    $display("-----------------------------------------------------------------");
  end
  initial begin
    #20 $finish;
  end   
endmodule


  Simulator output:  
     -----------------------------------------------------------------
           Value of a=0
           Value of a=1
           Value of a=2
           Value of a=3
     $finish called from file "testbench.sv", line 27.
     $finish at simulation time                   20
Execute the above code on