SystemVerilog Overriding class members

Overriding class members


Base class or parent class properties and methods can be overridden in the child class or extended class.

Defining the class properties and methods with the same name as parent class in the child class will override the class members.

Overriding class member example


In below example,

The parent class has the method display().
display() method is re-defined in the child class, which will override the parent class method.
c is the handle to the child class, because of override calling c.display will call display method of the child class, not the parent class.

class parent_class;
  bit [31:0] addr;

  function display();
    $display("Addr = %0d",addr);
  endfunction
endclass

class child_class extends parent_class;
  bit [31:0] data;
  function display();
    $display("Data = %0d",data);
  endfunction
endclass

module inheritence;
  initial begin
    child_class c=new();
    c.addr = 10;
    c.data = 20;
    c.display();
  end
endmodule

 Simulator Output  

Data = 20
Execute the above code on