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SystemVerilog Inline Constraints

Inline Constraints in SystemVerilog


Constraints will be written inside the class. inline constraint allows the user to add extra constraints to existing constraints written inside the class. inline constraints will be written outside the class i.e along with the randomize method call.

  • the inline constraint is written using with keyword
  • during randomization, constraint solver will consider both inline constraints and constraints written inside the class
  • the inline constraint will not override the constraints written inside the class
  • the inline constraint shouldn't conflict with the constraint written inside the class, else it will lead to randomization failure
    • for example, constraint inside the class written as var < 5, and inline constraint written as var > 5

Inline constraint Syntax


object.randomize() with { .... };

Inline constraint examples


Only inline constraint


In the below example,
Class doesn't have constraints defined in it. the inline constraint is used to constrain the variable addr.

class packet;
  rand bit [3:0] addr;
endclass

module inline_constr;
  initial begin
    packet pkt;
    pkt = new();

    repeat(2) begin
      pkt.randomize() with { addr == 8;};
      $display("\taddr = %0d",pkt.addr);
    end
  end
endmodule

 Simulator Output 

addr = 8
addr = 8
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Constraint inside the class and inline constraint


In the below example,
addr and data are the two random variables. The constraint for data is written inside the class, and the inline constraint is written for addr.

Conclusion: Both class and inline constraints are considered during randomization.

class packet;
  rand bit [3:0] addr;
  rand bit [3:0] data;

  constraint data_range { data > 0;
                          data < 10; }
endclass

module inline_constr;
  initial begin
    packet pkt;
    pkt = new();
    repeat(2) begin
      pkt.randomize() with { addr == 8;};
      $display("\taddr = %0d data = %0d",pkt.addr,pkt.data);
    end
  end
endmodule

 Simulator Output 

addr = 8 data = 2
addr = 8 data = 5
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Conflict with inline constraint


In the below example,
The addr is the random variable. constraint inside the class written as addr < 5, and inline constraint written as addr > 5.

Conclusion: Conflict between the class and inline constraints leads to randomization failure.

class packet;
  rand bit [3:0] addr;
  
  constraint addr_range {addr < 5;};
endclass

module inline_constr;
  initial begin
    packet pkt;
    pkt = new();
    repeat(2) begin
      pkt.randomize() with { addr > 5;};
      $display("\taddr = %0d",pkt.addr);
    end
  end
endmodule

 Simulator Output 

Error-[CNST-CIF] Constraints inconsistency failure
testbench.sv, 15
  Constraints are inconsistent and cannot be solved.
  Please check the inconsistent constraints being printed above and rewrite
  them.
addr = 0
=======================================================
Solver failed when solving following set of constraints
rand bit[3:0] addr; // rand_mode = ON
constraint addr_range    // (from this) (constraint_mode = ON) (testbench.sv:7)
{
   (addr < 4'h5);
}
constraint WITH_CONSTRAINT    // (from this) (constraint_mode = ON) (testbench.sv:15)
{
   (addr > 4'h5);
}
=======================================================

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Class and inline constraints for the same random variable


In the below example,
The addr is the random variable. constraint inside the class written as addr between 6:12, and inline constraint is written as addr == 8.

Conclusion: Constraint solver considers both class and inline constraints.

class packet;
  rand bit [3:0] addr;
  
  constraint addr_range {addr inside {[6:12]};};
endclass

module inline_constr;
  initial begin
    packet pkt;
    pkt = new();
    repeat(2) begin
      pkt.randomize() with { addr == 8;};
      $display("\taddr = %0d",pkt.addr);
    end
  end
endmodule

 Simulator Output 

addr = 8
addr = 8

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