SystemVerilog Functions

  functions 


A Function can contain declarations of range, returned type, parameters, input arguments, registers and events. A function without a range or return type declaration, returns a one-bit value.
Any expression can be used as a function call argument. Functions cannot contain any time-controlled statements, and they cannot enable tasks. Functions can return only one value.

SystemVerilog function can be static or automatic. Static functions share the same storage space for all task calls.Automatic functions allocate unique, stacked storage for each task call.

SystemVerilog allows,
1.to declare automatic variable in static functions and static variable in automatic functions
 2.more capabilities for declaring function ports
3.multiple statements within function without requiring a begin...end or fork...join block
 4.returning from function before reaching the end of function
 5.Passing values by reference, value, names and position
 6.Default argument values
 7.Function output and inout ports
 8.Default direction of argument is input if no direction has been specified.
 9.Default arguments type is logic if no type has been specified.

  Example-1:  

In below example,
arguments in parentheses.

module sv_function;
  int x;
  //function to add two integer numbers.
  function int sum(input int a,b);
    sum = a+b;   
  endfunction

  initial begin
    x=sum(10,5);
    $display("\tValue of x = %0d",x);
  end
endmodule


  Simulator output:  

       Value of x=15
Execute the above code on 

  Example-2:  

In below example,
arguments in declarations and directions.

module sv_function;
  int x;

  //function to add two integer numbers.
  function int sum;
    input int a,b;
    sum = a+b;   
  endfunction
  initial begin
    x=sum(10,5);
    $display("\tValue of x = %0d",x);
  end
endmodule


  Simulator output:  

       Value of x = 15
Execute the above code on 

  Example-3:  


In the below example,
arguments in declarations and directions, return value is specified using return statement.

module sv_function;
  int x;

  //function to add two integer numbers.
  function int sum;
    input int a,b;
    return a+b;   
  endfunction

  initial begin
    x=sum(10,5);
    $display("\tValue of x = %0d",x);
  end
endmodule


 Simulator Output  

Value of x = 15
Execute the above code on 

  Example-4:  


The example below shows usage of void function, void function,(function with no return value)

module sv_function;
  int x;
 
  //void function to display current simulation time 
  function void current_time;
    $display("\tCurrent simulation time is %0d",$time);    
  endfunction
 
  initial begin
    #10;
    current_time();
    #20;
    current_time();
  end
endmodule


 Simulator Output  


Current simulation time is 10
Current simulation time is 30
Execute the above code on 


  Example-5:  



The example below shows, discarding function return value.
Function return value must be assigned to variable or used in an expression, calling a function as if it has no return value can result a warning message. systemverilog void data type is used to discard a function's return value without any warning message.


module sv_function;
  int x;
   //function to add two integer numbers. 
  function int sum;
    input int a,b;
    return a+b;    
  endfunction
 
  initial begin
    $display("Calling function with void");
    void'(sum(10,5));
  end
 endmodule



 Simulator Output  

Calling function with void
Execute the above code on 

  Example-6:  


The example below shows, function call as an expression.

module sv_function;
  int x;
  //function to add two integer numbers. 
  function int sum;
    input int a,b;
  return a+b;    
  endfunction
  initial begin
    x = 10 + sum(10,5);
    $display("\tValue of x = %0d",x);
  end
endmodule

 Simulator Output  

Value of x = 25
Execute the above code on