SystemVerilog For loop


  for loop 


systemverilog for loop is enhanced for loop of verilog, 
in verilog, control variable of loop must be declared before the loop. verilog allows single initial declaration and single step assignment within the for loop.

SystemVerilog for loop allows,
1.declaration of loop variable within the for loop.
2.one or more initial declaration or assignment within the for loop.
3.one or more step assignment within the for loop.


  Example-1:  


In the below example, shows the declaration of loop variable within the for loop.

module for_loop;
  initial begin
    $display("-----------------------------------------------------------------");
    for(int i=0;i<5;i++) $display("\t Value of i = %0d",i);
    $display("-----------------------------------------------------------------");
  end  
endmodule

  Simulator output:  
      -----------------------------------------------------------------
       Value of i = 0
       Value of i = 1
       Value of i = 2
       Value of i = 3
       Value of i = 4
      -----------------------------------------------------------------

Execute the above code on 


  Example-2:  



below example shows,
one or more initial declaration within the for loop.

module for_loop;

  initial begin
    $display("-----------------------------------------------------------------");
 
    for ( int j=0,i=4;j<8;j++) begin
      if(j==i) $display("\tValue j equals to Value of i. j=%0d i=%0d",j,i);
    end
 
    $display("-----------------------------------------------------------------");
  end
   
endmodule

  Simulator output:  
      -----------------------------------------------------------------
            Value j=4 equals to Value of i=4
      -----------------------------------------------------------------

Execute the above code on 


  Example-3:  


below example shows,
one or more step assignment within the for loop.

module for_loop;

  initial begin
    $display("-----------------------------------------------------------------");
  
    for ( int j=0,i=7;j<8;j++,i--) begin
      $display("\tValue j=%0d Value of i=%0d",j,i);
    end

    $display("-----------------------------------------------------------------");
  end
   
endmodule

  Simulator output:  
      -----------------------------------------------------------------
            Value j equals to Value of i. j=0 i=7
            Value j equals to Value of i. j=1 i=6
            Value j equals to Value of i. j=2 i=5
            Value j equals to Value of i. j=3 i=4
            Value j equals to Value of i. j=4 i=3
            Value j equals to Value of i. j=5 i=2
            Value j equals to Value of i. j=6 i=1
            Value j equals to Value of i. j=7 i=0
-----------------------------------------------------------------

Execute the above code on