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SystemVerilog For loop

for loop


SystemVerilog for loop is enhanced for loop of Verilog.

In Verilog, 
  • the control variable of the loop must be declared before the loop
  • allows only a single initial declaration and single step assignment within the for a loop

SystemVerilog for loop allows,
  • declaration of a loop variable within the for loop
  • one or more initial declaration or assignment within the for loop
  • one or more step assignment or modifier within the for loop

for loop syntax


for(initialization; condition; modifier) begin 
  //statement - 1
  ...
  //statement - n
end

Initialization: executed first, and only once. This allows the user to declare and initialize loop control variables.

Condition: the condition is evaluated. If it is true, the body of the loop is executed, else the flow jumps to the statement after the 'for' loop.

Modifier: at the end of each iteration it will be executed, and execution moves to Condition.  

for loop example 


Below example shows the declaration of a loop variable within the for loop.

module for_loop;
  initial begin
    $display("-----------------------------------------------------------------");
    for(int i=0;i<5;i++) $display("\t Value of i = %0d",i);
    $display("-----------------------------------------------------------------");
  end  
endmodule

  Simulator output:  
      -----------------------------------------------------------------
       Value of i = 0
       Value of i = 1
       Value of i = 2
       Value of i = 3
       Value of i = 4
      -----------------------------------------------------------------

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multiple initializations in for loop


Below example shows the declaration and initialization of two variables i and j in for loop.

module for_loop;

  initial begin
    $display("-----------------------------------------------------------------");
 
    for ( int j=0,i=4;j<8;j++) begin
      if(j==i) $display("\tValue j equals to Value of i. j=%0d i=%0d",j,i);
    end
 
    $display("-----------------------------------------------------------------");
  end
   
endmodule

  Simulator output:  
      -----------------------------------------------------------------
            Value j=4 equals to Value of i=4
      -----------------------------------------------------------------

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multiple modifiers in for loop


Below example shows the use of two modifiers j++ and i-- within the for loop.

module for_loop;

  initial begin
    $display("-----------------------------------------------------------------");
  
    for ( int j=0,i=7;j<8;j++,i--) begin
      $display("\tValue j=%0d Value of i=%0d",j,i);
    end

    $display("-----------------------------------------------------------------");
  end
   
endmodule

  Simulator output:  
      -----------------------------------------------------------------
            Value j equals to Value of i. j=0 i=7
            Value j equals to Value of i. j=1 i=6
            Value j equals to Value of i. j=2 i=5
            Value j equals to Value of i. j=3 i=4
            Value j equals to Value of i. j=4 i=3
            Value j equals to Value of i. j=5 i=2
            Value j equals to Value of i. j=6 i=1
            Value j equals to Value of i. j=7 i=0
-----------------------------------------------------------------

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