SystemVerilog Coverage


Coverage is used to measure  tested and untested portions of the design. Coverage is defined as the percentage of verification objectives that have been met.

There are two types of coverage metrics.
  • Code Coverage
  • Functional Coverage

 Code Coverage 

Code coverage measures how much of  the “design Code” is exercised.
This includes, execution of design blocks, Number of Lines, Conditions, FSM, Toggle and Path.

Simulator tool will automatically extracts the code coverage from the design code.

 Functional Coverage 

Functional coverage is a user-defined metric that measures how much of the design specification has been exercised in verification.

There are two types of functional coverage,

  • Data-oriented Coverage  - Checks combinations of data values have occurred. We can get Data-oriented coverage by writing Coverage groups, coverage points and also by cross coverage.
  • Control-oriented Coverage - Checks whether sequences of behaviors have occurred. We can get assertion coverage by writing SystemVerilog Assertions.
Defining the functional coverage is covered in next chapters.