SystemVerilog Constraint inside

 Inside Operator 


With inside operator, random variables will get values specified within the block followed by inside operator.
values within the inside block can be variable, constant or range.

      constraint addr_range { addr inside {1,3,5,7,9}; }
      constraint addr_range { addr inside {[5:10]}; }
      constraint addr_range { addr inside {1,3,[5:10],12,[13:15]}; }
      constraint addr_range { addr !(inside {[5:10]}); }

       rand bit [3:0] start_addr;
       rand bit [3:0] end_addr;
       rand bit [3:0] addr;
       constraint addr_range { addr inside {[start_addr:end_addr]}; }

 Example-1: 


In the example below,
  addr_1 will get random value within the range start_addr and end_addr,
  addr_2 will get random value out of start_addr and end_addr.

class packet;
  rand bit [3:0] addr_1;
  rand bit [3:0] addr_2;
  rand bit [3:0] start_addr;
  rand bit [3:0] end_addr;
  constraint addr_1_range {   addr_1 inside {[start_addr:end_addr]}; }
  constraint addr_2_range { !(addr_2 inside {[start_addr:end_addr]}); }
endclass

module constr_inside;
  initial begin
    packet pkt;
    pkt = new();

    $display("------------------------------------");
    repeat(3) begin
      pkt.randomize();
      $display("\tstart_addr = %0d,end_addr = %0d",pkt.start_addr,pkt.end_addr);
      $display("\taddr_1 = %0d",pkt.addr_1);
      $display("\taddr_2 = %0d",pkt.addr_2);
      $display("------------------------------------");
    end
  end
endmodule

 Simulator Output  

------------------------------------
start_addr = 12,end_addr = 12
addr_1 = 12
addr_2 = 4
------------------------------------
start_addr = 3,end_addr = 7
addr_1 = 6
addr_2 = 8
------------------------------------
start_addr = 7,end_addr = 11
addr_1 = 7
addr_2 = 6
------------------------------------
Execute the above code on