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SystemVerilog Constraint inside

Constraint inside SystemVerilog


During randomization, it might require to randomize the variable within a range of values or with inset of values or other than a range of values. this can be achieved by using constraint inside operator.With SystemVerilog inside operator, random variables will get values specified within the inside block.
  • values within the inside block can be variable, constant or range
  • the inside block is written with an inside keyword followed by curly braces {}
    constraint addr_range { addr inside { ... }; }
  • the range is specified by [ ]
    constraint addr_range { addr inside { [5:10]}; }
  • set of values are specified by 'comma',
    constraint addr_range { addr inside { 1,3,5,7,9}; }
  • it is allowed to mix range and set of values
    constraint addr_range { addr inside {1,3,[5:10],12,[13:15]}; }
  • if the value needs to be outside the range, then it can be specified as inverse (!) of inside
    constraint addr_range { addr !(inside {[5:10]}); }
  • Other random variables can be used in inside block
          rand bit [3:0] start_addr;
          rand bit [3:0] end_addr;
          rand bit [3:0] addr;
          constraint addr_range { addr inside {[start_addr:end_addr]}; }

constraint inside example


In the example below,
addr_1 will get random value within the range start_addr and end_addr,

class packet;
  rand bit [3:0] addr;
  rand bit [3:0] start_addr;
  rand bit [3:0] end_addr;
  
  constraint addr_1_range { addr inside {[start_addr:end_addr]}; }
endclass

module constr_inside;
  initial begin
    packet pkt;
    pkt = new();
    $display("------------------------------------");
    repeat(3) begin
      pkt.randomize();
      $display("\tstart_addr = %0d,end_addr = %0d",pkt.start_addr,pkt.end_addr);
      $display("\taddr = %0d",pkt.addr);
      $display("------------------------------------");
    end
  end
endmodule

 Simulator Output 

------------------------------------
start_addr = 12,end_addr = 13
addr = 12
------------------------------------
start_addr = 3,end_addr = 7
addr = 7
------------------------------------
start_addr = 5,end_addr = 11
addr = 9
------------------------------------

Execute the above code on 



inverted inside example


In the example below,
addr will get the random value outside the range start_addr and end_addr. this is done by using negation or invert operator (!)

class packet;
  rand bit [3:0] addr;
  rand bit [3:0] start_addr;
  rand bit [3:0] end_addr;
  
  constraint addr_1_range { !(addr inside {[start_addr:end_addr]}); }
endclass

module constr_inside;
  initial begin
    packet pkt;
    pkt = new();
    $display("------------------------------------");
    repeat(3) begin
      pkt.randomize();
      $display("\tstart_addr = %0d,end_addr = %0d",pkt.start_addr,pkt.end_addr);
      $display("\taddr = %0d",pkt.addr);
      $display("------------------------------------");
    end
  end
endmodule

 Simulator Output 

------------------------------------
start_addr = 12,end_addr = 4
addr = 0
------------------------------------
start_addr = 6,end_addr = 7
addr = 13
------------------------------------
start_addr = 5,end_addr = 9
addr = 11
------------------------------------
Execute the above code on