# Implication constraints and if else constraints in SystemVerilog

## Implication constraints

The implication operator can be used to declaring conditional relations between two variables. implication operator is denoted by the symbol ->. The implication operator is placed between the expression and constraint.

`expression -> constraint`

If the expression on the LHS of implication operator (->) is true, then the only constraint on the RHS will be considered.

### Implication constraint example

In the example below,
If addr_range == small, then addr will get a value less than 8.
i.e implication operator is used to mention condition between the two variables addr_range and addr.

```class packet;
```
```  constraint address_range { (addr_range == "small") -> (addr < 8);}
endclass

module constr_implication;
initial begin
packet pkt;
pkt = new();

\$display("------------------------------------");
repeat(4) begin
pkt.randomize();
end
\$display("------------------------------------");
end
endmodule```

Simulator Output

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Execute the above code on

## if else constraints

if else block allows conditional executions of constraints. If the expression is true, all the constraints in the first constraint/constraint-block must be satisfied, otherwise all the constraints in the optional else constraint/constraint-block must be satisfied.

### if else constraints example

Above an example of implication operator usage is written with if else condition.

In the example below,
If addr_range == small, then addr will get a value less than 8.

```class packet;

else
}
endclass

module constr_if_else;
initial begin
packet pkt;
pkt = new();
```
```    pkt.addr_range = "small";
\$display("------------------------------------");
repeat(3) begin
pkt.randomize();
end
\$display("------------------------------------");

\$display("------------------------------------");
repeat(3) begin
pkt.randomize();
end
\$display("------------------------------------");
end
endmodule```

Simulator Output
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