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Constrained randomization in SystemVerilog

Constrained randomization


As the name says random variable will get random value on randomization. In some situations it is required to control the values getting assigned on randomization, this can be achieved by writing constraints. By writing constraints to a random variable, the user can get specific value on randomization. constraints to a random variable shall be written in constraint blocks.

Constraint blocks


  • Constraint blocks are class members like tasks, functions, and variables
  • Constraint blocks will have a unique name within a class
  • Constraint blocks consist of conditions or expressions to limit or control the values for a random variable
  • Constraint blocks are enclosed within curly braces { }
  • Constraint blocks can be defined inside the class or outside the class like extern methods, constraint block defined outside the class is called as extern constraint block

Constraint block syntax


constraint <constraint_block_name> { <condition/expression>; 
                                              ...
                                    <condition/expression>; }

Constraint block examples


constraint addr_range { addr > 5; }

where, addr_range is constraint block name
            addr is constrained in such a way that on randomization addr will get a value greater than 5.

Constraint block inside the class


In the below example,
constraint block is defined inside the class.

class packet;
  rand  bit [3:0] addr;

  constraint addr_range { addr > 5; }
endclass

module constr_blocks;
  initial begin
    packet pkt;
    pkt = new();
    repeat(10) begin
      pkt.randomize();
      $display("\taddr = %0d",pkt.addr);
    end
  end
endmodule

 Simulator Output 

addr = 14
addr = 10
addr = 9
addr = 8
addr = 9
addr = 6
addr = 10
addr = 14
addr = 12
addr = 8

Execute the above code on 



Constraint block outside the class


In the below example,
constraint block is declared inside the class and defined outside the class.

class packet;
  rand  bit [3:0] addr;
  //constraint block declaration
  constraint addr_range;
endclass

//constraint implementation outside class body
constraint packet::addr_range { addr > 5; }

module extern_constr;
  initial begin
    packet pkt;
    pkt = new();

    repeat(10) begin
      pkt.randomize();
      $display("\taddr = %0d",pkt.addr);
    end
  end
endmodule

 Simulator Output 

addr = 14
addr = 10
addr = 9
addr = 8
addr = 9
addr = 6
addr = 10
addr = 14
addr = 12
addr = 8
Execute the above code on 



Constraint Inheritance


Like class members, constraints also will get inherited from parent class to child class. Constraint blocks can be overridden by writing constraint block with the same name as in parent class.

In the example below,
Constraint to an addr > 5 of the parent class is overridden with constraint addr < 5 in child class.

class packet;
  rand  bit [3:0] addr;
  constraint addr_range { addr > 5; }
endclass

class packet2 extends packet;
  constraint addr_range { addr < 5; } //overriding constraint of parent class
endclass

module const_inhe;
  initial begin
    packet pkt1;
    packet2 pkt2;

    pkt1 = new();
    pkt2 = new();

    $display("------------------------------------");
    repeat(5) begin
      pkt1.randomize();
      $display("\tpkt1:: addr = %0d",pkt1.addr);
    end

    $display("------------------------------------"); 
    repeat(5) begin
      pkt2.randomize();
      $display("\tpkt2:: addr = %0d",pkt2.addr);
    end
    $display("------------------------------------");
  end
endmodule

 Simulator Output 

------------------------------------
pkt1:: addr = 14
pkt1:: addr = 10
pkt1:: addr = 9
pkt1:: addr = 8
pkt1:: addr = 9
------------------------------------
pkt2:: addr = 0
pkt2:: addr = 1
pkt2:: addr = 2
pkt2:: addr = 0
pkt2:: addr = 2
------------------------------------

Execute the above code on