SystemVerilog Constraint Blocks

 Constraint blocks 


As the name says random variable will get random value on randomization, By writing constraints to an random variable, user can get specific value on randomization. constraints to an random variable shall be written in constraint blocks.

Constraint blocks are class members, like tasks, functions, and variables.each constraint block will have unique name within a class.
     constraint addr_range { addr > 5; }

where addr_range is constraint block name and addr is constrained in such a way that on randomization addr should get value greater than 5.

 External Constraint blocks 


External constraints are Same like external class methods.
constraint blocks can be defined outside the class body, declaration should be with in class body.

 Example-1: 


The Example below shows,
defining  of constraint block outside class body.

class packet;
  rand  bit [3:0] addr;

  constraint addr_range { addr > 5; }
endclass

module constr_blocks;
  initial begin
    packet pkt;
    pkt = new();
    repeat(10) begin
      pkt.randomize();
      $display("\taddr = %0d",pkt.addr);
    end
  end
endmodule

 Simulator Output  

addr = 14
addr = 10
addr = 9
addr = 8
addr = 9
addr = 6
addr = 10
addr = 14
addr = 12
addr = 8

Execute the above code on 

 Example-2: 


The Example below shows,
defining  of constraint block outside class body.

class packet;
  rand  bit [3:0] addr;
  //constraint block declaration
  constraint addr_range;
endclass

//constraint implementation outside class body
constraint packet::addr_range { addr > 5; }

module extern_constr;
  initial begin
    packet pkt;
    pkt = new();

    repeat(10) begin
      pkt.randomize();
      $display("\taddr = %0d",pkt.addr);
    end
  end
endmodule

 Simulator Output  
addr = 14
addr = 10
addr = 9
addr = 8
addr = 9
addr = 6
addr = 10
addr = 14
addr = 12
addr = 8

Execute the above code on 

 Constraint Inheritance 


As class members, constraints also will get inherited from parent class to child class. in a child class, constraint blocks can be overridden by writing constraint block with same name as in parent class.

 Example-1 : 


In the example below,
constraint to an addr > 5 of parent class is overridden with constraint addr < 5 in child class.

class packet;
  rand  bit [3:0] addr;
  constraint addr_range { addr > 5; }
endclass

class packet2 extends packet;
  constraint addr_range { addr < 5; } //overriding constraint of parent class
endclass

module const_inhe;
  initial begin
    packet pkt1;
    packet2 pkt2;

    pkt1 = new();
    pkt2 = new();

    $display("------------------------------------");
    repeat(5) begin
      pkt1.randomize();
      $display("\tpkt1:: addr = %0d",pkt1.addr);
    end

    $display("------------------------------------"); 
    repeat(5) begin
      pkt2.randomize();
      $display("\tpkt2:: addr = %0d",pkt2.addr);
    end
    $display("------------------------------------");
  end
endmodule

 Simulator Output  

------------------------------------
pkt1:: addr = 14
pkt1:: addr = 10
pkt1:: addr = 9
pkt1:: addr = 8
pkt1:: addr = 9
------------------------------------
pkt2:: addr = 0
pkt2:: addr = 1
pkt2:: addr = 2
pkt2:: addr = 0
pkt2:: addr = 2
------------------------------------
Execute the above code on