SystemVerilog Classes Inheritance

 Classes Inheritance 

New classes can be created based on existing classes.
A derived class by default inherits the properties and methods of its parent or base class.
    base class or parent class ->  existing class.
    derived class or child class    ->  New class.
the derived class may add new properties and methods, or modify the inherited properties and methods.

  Example - 1 

parent class properties is accessed using child class handle,i.e child class will have(inherit) parent class properties and methods.

class parent_class;
  bit [31:0] addr;
endclass

class child_class extends parent_class;
  bit [31:0] data;
endclass

module inheritence;
  initial begin
    child_class c = new();
    c.addr = 10;
    c.data = 20;
    $display("Value of addr = %0d data = %0d",c.addr,c.data);
  end
endmodule

 Simulator Output  
Value of addr = 10 data = 20

Execute the above code on