SystemVerilog break and continue

break and continue


break continue
systemverilog break continue

break


Execution of break statement leads to end of the loop.
break shall be used in all the loop constructs (while, do-while, foreach, for, repeat and forever).

syntax


break;

break in while loop


module break_in_while_loop;
  int i;
  
  initial begin
    $display("-----------------------------------------------------------------");
    i = 8;
    
    while(i!=0) begin
      $display("\tValue of i=%0d",i);
      if(i == 4) begin
        $display("\tCalling break,");
        break;
      end  
      i--;
    end
    
    $display("-----------------------------------------------------------------");
  end      
endmodule

 Simulator output: 

-----------------------------------------------------------------
Value of i=8
Value of i=7
Value of i=6
Value of i=5
Value of i=4
Calling break,
-----------------------------------------------------------------
Execute the above code on 

break in do while loop


module break_in_do_while_loop;
  int i;
  
  initial begin
    $display("-----------------------------------------------------------------");
    i = 8;
    
    do begin
      $display("\tValue of i=%0d",i);
      if(i == 4) begin
        $display("\tCalling break,");
        break;
      end  
      i--;
    end
    while(i!=0);

    
    $display("-----------------------------------------------------------------");
  end      
endmodule

 Simulator output: 

-----------------------------------------------------------------
Value of i=8
Value of i=7
Value of i=6
Value of i=5
Value of i=4
Calling break,
-----------------------------------------------------------------
Execute the above code on 




break in foreach loop


module foreach_loop_break;
  int a[4];
  
  initial begin
    $display("-----------------------------------------------------------------");
    
    foreach(a[i]) a[i] = i;
    foreach(a[i]) begin
      $display("\tValue of a[%0d]=%0d",i,a[i]);
      if(i == 2) begin
        $display("\tCalling break,");
        break;
      end  
    end      
    
    $display("-----------------------------------------------------------------");
  end     
endmodule

 Simulator output: 

-----------------------------------------------------------------
Value of a[0]=0
Value of a[1]=1
Value of a[2]=2
Calling break,
-----------------------------------------------------------------
Execute the above code on 




break in for loop

In below example,
when the loop value equals to 4, break is called this leads to end of the loop.

module break_in_loop;

  initial begin
    $display("-----------------------------------------------------------------"); 

    for(int i=0;i<8;i++) begin
      $display("\tValue of i=%0d",i);
      if(i == 4) begin
        $display("\tCalling break,");
        break;
      end 
    end  

    $display("-----------------------------------------------------------------");
  end

endmodule

 Simulator output: 

-----------------------------------------------------------------
      Value of i=0
      Value of i=1
      Value of i=2
      Value of i=3
      Value of i=4
      Calling break,
-----------------------------------------------------------------
Execute the above code on 

break in repeat loop


module repeat_loop_break;
  int i;
  
  initial begin
    $display("-----------------------------------------------------------------");
    
    repeat(5) begin
      $display("\tValue of i=%0d",i);
      if(i == 2) begin
        $display("\tCalling break,");
        break;
      end  
      i++;
    end      
    
    $display("-----------------------------------------------------------------");
  end     
endmodule

 Simulator output: 

-----------------------------------------------------------------
Value of i=0
Value of i=1
Value of i=2
Calling break,
-----------------------------------------------------------------
Execute the above code on 




break in forever loop


module forever_loop_break;
  int i;
  
  initial begin
    $display("-----------------------------------------------------------------");
    
    i = 5;
    forever begin
      $display("\tValue of i=%0d",i);
      if(i == 2) begin
        $display("\tCalling break,");
        break;
      end  
      i++;
    end      
    
    $display("-----------------------------------------------------------------");
  end     
endmodule

 Simulator output: 

-----------------------------------------------------------------
Value of i=0
Value of i=1
Value of i=2
Calling break,
-----------------------------------------------------------------
Execute the above code on 




Continue in SystemVerilog


Execution of continue statement leads to skip the execution of statements followed by continue and jump to next loop or iteration value.

syntax


continue;

Continue example


In below example,

when ever the loop value is with in 3 to 6, continue statement will be executed, this leads to skip the execution of display statement after the continue.
module continue_in_loop;

  initial begin
    $display("-----------------------------------------------------------------");
 
    for(int i=0;i<8;i++) begin     

      if((i > 2) && (i < 7))begin
        $display("\t\tCalling continue,");
        continue;
      end   

      $display("\t\tAfter Continue\t:: Value of i=%0d",i);
    end

    $display("-----------------------------------------------------------------");

  end

endmodule


  Simulator output:  

-----------------------------------------------------------------
After Continue :: Value of i=0
After Continue :: Value of i=1
After Continue :: Value of i=2
Calling continue,
Calling continue,
Calling continue,
Calling continue,
After Continue :: Value of i=7
-----------------------------------------------------------------
Execute the above code on