SystemVerilog Assertions

 SystemVerilog Assertions (SVA) 


Assertions are primarily used to validate the behavior of a design. An assertion is a check embedded in, or bound to a design unit during simulation.Warnings or errors are generated on failure of specific condition or sequence of events.

Assertions are used to,
  • Check the occurrence of specific condition or sequence of events.
  • Provide functional coverage.
There are two kinds of assertions:
  • Immediate Assertions
  • Concurrent Assertions

 Immediate Assertions: 


Immediate assertions check for a condition at the current simulation time.

An immediate assertion is same as an if..else statement, but with assertion control. Immediate assertions have to be placed in a procedural block definition.

A simple immediate assertion is shown below,
The always block executes if either signal "a" or signal "b" changes.

          always  a: assert (a && b ) ;


assert can be used as below,

          assert(condition) $display(“Condition is True”); else $display(“Condition is False”);

          assert(condition) $display(“Condition is True”);

          assert(condition) $(“Condition is True”); else $fatal(“Condition is False”);

          assert(condition)
            else begin
               …….
               …….
              $fatal(“Condition is False”);
            end

          assert(condition) else $warning(“Condition is False”);

          label: assert(condition) else $warning(“Condition is False”);

If an assertion fails and no else clause is specified, the tool shall, by default call $error.


 Concurrent Assertions: 


Concurrent assertions check the sequence of events spread over multiple clock cycles.
  • Concurrent assertion is evaluated only at the occurrence of a clock tick.
  • Test expression is evaluated at clock edges based on the sampled values of the variables involved..
  • Can be placed in a procedural block, a module, an interface or a program definition.

   c_assert:  assert property(@(posedge clk) not(a && b));

The Keyword differentiates the immediate assertion from the concurrent assertion is "property."