Before moving to SystemVerilog concepts, we will look into what is Verification? What is verified? Why do we need to verify it? How to Verify?
We need to verify the design to make sure that the design is an accurate representation of the specification without any bugs. Verification is carried out to ensure the correctness of design, to avoid surprises at a later time, to avoid a re-spin of the chip and to enter the market on time with good quality.
In the process of verification, we are going to verify modules, SOC’s (System On Chip) by driving the input to check the design behavior. we should check the behavior of the design by driving correct and an error input, in both cases need to observe the design as it is behaving as expected, if not then there will be a bug.
In verification, we use the Testbench/Verification environment to determine the correctness of the design under test (DUT).
below is the functionality of the Testbench/Verification environment,
- Generate stimulus
- Apply stimulus to the DUT
- Capture the response
- Check for the correctness
- Measure progress against the overall verification goals
SystemVerilog concepts and methods are explained in the upcoming chapters. The content herein the SystemVerilog tutorial is just for quick reference, for more detailed explanation refer to SystemVerilog LRM.
an added advantage of referring Verification Guide SystemVerilog tutorial is,
- 100+ easy understanding, compilation error-free example codes.
- While going through the tutorial no need to copy example code to your simulator, Just One Click for the execution of example codes. All the example codes are saved in the EDA playground.
Thanks to doulos for providing the free access and an option to share the codes on 
(EDA playground).
