Before moving to SystemVerilog concepts, we will look in to what is Verification?  What is verified? Why do we need to verify? How to Verify?

We need to verify the design to make sure that the design is an accurate representation of the specification without any bugs. Verification is carried out to ensure correctness of design, to avoid surprises at a later time, to avoid a re-spin of the chip and to enter the market on time with good quality.

In the process of verification we are going to verify modules, SOC’s (System On Chip) by driving the input to check the design behavior. we should check the behavior of the design by driving correct and error input, in both the cases need to  observe  the design as it is behaving as expected, if not then there will be an bug.

In verification we use Testbench/Verification environment to determine the correctness of the design under test (DUT).
below are the functionality of the Testbench/Verification environment,
  • Generate stimulus
  • Apply stimulus to the DUT
  • Capture the response
  • Check for the correctness
  • Measure progress against the overall verification goals

SystemVerilog concepts and methods are explained in the upcoming chapters.The content here in SystemVerilog tutorial is just for quick reference, for more detailed explanation refer to SystemVerilog LRM.

added advantage of referring Verification Guide SystemVerilog tutorial is,
  • 100+ easy understanding, compilation error free example codes.
  • While going through the tutorial no need to copy example code to your simulator, Just One Click for execution of example codes. All the example codes are saved in EDA playground.
Thanks to   (doulos)  for providing the free access and option to share the codes on   (EDA playground).