UVM Testbench

 UVM TestBench/TB 


UVM testbenchs are constructed by extending uvm classes. 

below is the typical UVM testbench hierarchy diagram.

Typical UVM TestBench Hierarchy
*click on image for better view

Role of each testbench element is,

 Test 

This is the top most class. test is responsible for, 
  • configuring the testbench.
  • initiate the testbench components construction process by building the next level down in the hierarchy ex: env.
  • initiate the stimulus by starting the sequence.

 Environment or Env 


The environment is a container component for grouping higher level components like agent's and scoreboard.

 Agent 


UVM agent groups the uvm_components specific to an interface or protocol.
example: groups the components associated with BFM(Bus Functional Model).

The components of agent are,


  •  Sequence item: 
Sequence item defines the pin level activity generated by agent (to drive to DUT through the driver) or the activity has to be observed by agent (Placeholder for the activity monitored by monitor on DUT signals).


  •  Driver: 
Responsible for driving the packet level data inside sequence_item into pin level (to DUT).


  •  Sequence: 
Defines the sequence in which the data items need to be generated and sent/received to/from driver.

  •  Sequencer: 
Responsible for routing the data packet's(sequence_item) generated in sequence to the driver or vice verse.


  •  Monitor: 
Observes pin level activity on interface signals and converts into packet level which are sent to components such as scoreboards.

 Scoreboard 

Receives data item's from monitor's and compares with expected values.
expected values can be either golden reference values or generated from reference model.


Detailed explanation of each component and methods assosiated with each is described in next page onwords.

For the easy understanding of UVM Concepts, Memory Model example explained in Writing SystemVerilog Testbench is considered.


 UVM TestBench Block Diagram 

  • UVM TestBench Block Diagram with single agent.


UVM TestBench block diagram with single agent
*click on image for better view

  • UVM TestBench Block Diagram with multiple agent's and multiple instance of each.


UVM TestBench block diagram with multiple agents
*click on image for better view