UVM Objection / Managing End of Test

 UVM Objection 

UVM provides an objection mechanism to allow hierarchical status communication among components which is helpful in deciding the end of test.

There is a built-in objection for each phase, which provides a way for components and objects to synchronize their testing activity and indicate when it is safe to end the phase and, ultimately, the test end.

The component or sequence will raise a phase objection at the beginning of an activity that must be completed before the phase stops, so the objection will be dropped at the end of that activity. Once all of the raised objections are dropped, the phase terminates.

Lets consider an example,
A master agent may need to complete all its write and read operations before the run phase should be allowed to stop.
In this example, typically objections can either be added in sequence or test.

Objection in sequence,
objection is raised when it started as a root sequence (a sequence which has no parent sequence), and to drop the objection when it is finished as a root sequence.

class wr_rd_seq extends uvm_sequence#(mem_seq_item);
  task pre_body();
    // raise objection if started as a root sequence
    if(starting_phase != null)

  task body();

  task post_body();
    // drop objection if started as a root sequence
    if(starting_phase != null)

The starting_phase member is only set automatically if the sequence is started as the default sequence
for a particular phase. so objections were used in the sequence if it is default sequence for a particular phase.

Objection in test,
If the sequence need to be started explicitly i.e in the test, then the objections were added in the test instead of sequence

class wr_rd_test extends uvm_test;
  task main_phase(uvm_phase phase);
    phase.raise_objection(); //rasing objection
    phase.drop_objection();  //droping objection

When the sequence is started explicitly, the starting_phase member is null, so the sequence will not raise or drop the phase objection.