Introduction to UVM
The Universal Verification Methodology (UVM) consists of class libraries needed for the development of well constructed, reusable SystemVerilog based Verification environment.
In simple words, UVM consists of set of base classes with methods defined in it, SystemVerilog verification environment can be developed by extending these base classes.
Now on will refer the UVM base classes as UVM Classes,
UVM consists of three main types of UVM classes,
- Core class based operational methods (create, copy, clone, compare, print, record, etc..), instance identification fields (name, type name, unique id, etc.) and random seeding were defined in it.
- All uvm_transaction and uvm_component were derived from uvm_object.
- Used in stimulus generation and analysis.
- Components are quasi-static objects that exist throughout simulation.
- Every uvm_component is uniquely addressable via a hierarchical path name, e.g. “env.agent.driver”.
- The uvm_component also defines a phased test flow, that components follow during the course of simulation. Each phase(build, connect, run, etc.) is defined by a callback that is executed in precise order.
- The uvm_component also defines configuration, reporting, transaction recording, and factory interfaces.