UVM Interview Questions

Below are the most frequently asked UVM Interview Questions,

  1. What is uvm_transaction, uvm_seq_item, uvm_object, uvm_component?
  2. What is the advantage of  `uvm_component_utils() and `uvm_object_utils() ?
  3. What is the difference between `uvm_do and `uvm_ran_send?
  4. diff between uvm_transaction and uvm_seq_item?
  5. What is the difference between uvm _virtual_sequencer and uvm_sequencer ?
  6. What are the benefits of using UVM?
  7. What is super keyword? What is the need of calling super.build() and super.connect()?
  8. Is uvm is independent of systemverilog ?
  9. Can we have user defined phase in UVM?
  10. What is p_sequencer ?
  11. What is uvm RAL model ? why it is required ?
  12. What is the difference between new() and create?
  13. What is analysis port?
  14. What is TLM FIFO?
  15. How sequence starts?
  16. What is the difference between UVM RAL model backdoor write/read and front door write/read ?
  17. What is objection?
  18. What is the advantage of `uvm_pre_body and `uvm_post_body ?
  19. What is the difference between Active mode and Passive mode?
  20. What is the difference between copy and clone?
  21. What is UVM factory? 
  22. What are the types of sequencer? Explain each?
  23. What are the different phases of uvm_component? Explain each?
  24. How set_config_* works?
  25. Ehat are the advantages of uvm RAL model ?
  26. What is the different between set_config_* and uvm_config_db ?
  27. What  are the different  override types?
  28. What is virtual sequence and virtual sequencer?
  29. Explain end of simulation in UVM?
  30. How to declare multiple imports?
  31. What is symbolic representation of port, export and analysis port?
  32. What is the difference in usage of $finish and global stop request in UVM?
  33. Why we need to register class with uvm factory?
  34. can we use set_config and get_config in sequence ?
  35. What is uvm_heartbeat ?
  36. how to access DUT signal in uvm_component/uvm_object ?