Abstract Class
Table of Contents
SystemVerilog class declared with the keyword virtual is referred to as an abstract class.
- An abstract class sets out the prototype for the sub-classes.
- An abstract class cannot be instantiated, it can only be derived.
- An abstract class can contain methods for which there are only a prototype and no implementation, just a method declaration.
Abstract class Syntax
virtual class abc; //Class defination endclass
Abstract Class Examples
Instantiating virtual class
In the below example, Creating an object of a virtual class. An abstract class can only be derived, creating an object of a virtual class leads to a compilation error.
//abstract class virtual class packet; bit [31:0] addr; endclass module virtual_class; initial begin packet p; p = new(); end endmodule
Simulator Output
virtual_class, "p = new();" Instantiation of the object 'p' can not be done because its type 'packet' is an abstract base class. Perhaps there is a derived class that should be used.
Deriving virtual class
In the below example, An abstract class is derived and written extend the class and creating it.
//abstract class
virtual class packet;
bit [31:0] addr;
endclass
class extended_packet extends packet;
function void display;
$display("Value of addr is %0d", addr);
endfunction
endclass
module virtual_class;
initial begin
extended_packet p;
p = new();
p.addr = 10;
p.display();
end
endmodule
Simulator Output
Value of addr is 10
